1. Technical Field
The present disclosure is directed to methods of planarizing polysilicon patterns and methods of manufacturing a semiconductor device using the same. More particularly, the present disclosure is directed to methods of planarizing polysilicon patterns having an improved planarity within a substrate and between substrates and methods of manufacturing a semiconductor device using the same.
2. Description of the Related Art
A logic circuit transistor may be formed through a gate first process wherein a gate electrode may be patterned first before forming source/drain electrodes, etc., or through a gate last process wherein the gate electrode may be formed in the last process.
In particular, when a gate electrode is formed using a metal, directly patterning the metal may be challenging and so a gate last process may be used. When a gate electrode is formed using a gate last process, a planarization process may be stably performed to provide the gate electrodes with a uniform height. In addition, during planarization, damage to other patterns formed around the gate electrode or the generation of dishing defects should be minimized.